Flash memories are widely used in numerous applications. A conventional flash memory permits a group of memory cells or a memory block to be simultaneously programmed (e.g., written) and/or erased through a single operation. Data may be written to and/or erased from a memory cell for a finite number of times. A flash memory usually has a large number of memory blocks, and if data is written to and/or erased from memory cells of one or more specific group of memory blocks repeatedly, those memory blocks may wear out relatively faster. Thus, it may be desirable that data be distributed evenly across all the memory blocks of a memory. In this way, no single memory block or a group of memory blocks may prematurely fail due to a high number of write and/or erase cycles. This process decreases the total wear on the memory, thereby increasing the lifetime of the memory. A wear—leveling table is usually used to determine the memory blocks to which data is to be written, so that the number of write and erase cycles are almost evenly distributed across all memory blocks of a memory.
FIG. 1 schematically illustrates an exemplary memory module 100 that includes a plurality of memory blocks 1, . . . , H. Each of the memory blocks 1, . . . , H includes one or more memory cells. FIG. 2 illustrates an exemplary wear—leveling table 200 associated with the memory module 100. Each row of the wear—leveling table 200 is associated with a corresponding memory block of FIG. 1, and includes the memory block identification number and a number of times the memory block (e.g., one or more cells of the memory block) has undergone data write—erase cycles. For example, the first row of the wear—leveling table 200 illustrates that memory block 1 of FIG. 1 has undergone 4,000 write—erase cycles. That is, data has been written to and/or erased from one or more memory cells of the memory block 1 for 4,000 times. Similarly, the last row of the wear—leveling table 200 illustrates that memory block H of FIG. 1 has undergone 5,000 write—erase cycles. Accordingly, if new data has to be written to the memory module 100, the new data may be written preferably in memory block 1 instead of memory block H (or a memory block that has undergone a lower (e.g., the lowest) number of write—erase cycles), so that the number of write—erase cycles is almost evenly distributed across the memory blocks.
Flash memories usually store data in individual memory cells, and the memory cells are usually made of floating-gate transistors. In a single-level cell (SLC) flash memory, one bit of data is stored in each cell. A multi-level cell (MLC) flash memory, on the other hand, stores more than one bit of data in each cell, with the “multi-level” referring to the multiple levels of electrical charge used to store multiple bits per memory cell.
SLC cells usually have relatively faster transfer speed and lower power consumption than MLC cells. However, as SLC cells store less data per cell, cost per megabyte of SLC storage is usually more (e.g., around three times) than MLC storage.
Also, SLC cells may withstand a larger number of write and/or erase cycles as compared to MLC cells. For example, a typical SLC cell may withstand about 100,000 erase-write cycles on an average before wear begins to deteriorate the integrity of the storage, whereas a typical MLC cell may withstand about 10,000 write and/or erase cycles.